Intel 80C188XL - Manual (Page 119)

BUS INTERFACE UNIT
3-38
In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre-
cede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are
not acknowledged until the instruction following the prefix completes (except for instructions
that are servicing interrupts during their execution, such as HALT, WAIT and repeated string
primitives).Note that multiple prefix bytes can precede an instruction.
Another example is a string primitive preceded by the repetition prefix (REP), which can be in-
terrupted after each execution of the string primitive, even if the REP prefix is combined with the
LOCK prefix. This prevents interrupts from being locked out during a block move or other re-
peated string operations. However, bus hold, DMA and refresh requests remain locked out until
LOCK is removed (either when the block operation completes or after an interrupt occurs.
3.6.4 Using the Queue Status Signals
Older-generation devices require the queue status signals to interface with an 8087 math copro-
cessor. Newer devices do not require these signals because they use the 80187 math coprocessor,
which has an I/O port interface similar to that of a peripheral device.
The queue status signals, QS0 and QS1, indicate the state of the internal queue (Table 3-7). Since
the Execution Unit can remove information from the queue on any clock boundary, the queue sta-
tus pins may change state on every phase 1 clock edge (Figure 3-33). Although these signals can-
not be related to any specific T-state, the relationship between the queue status signals and BIU
operation always remains the same for a given instruction sequence.
QS0 and QS1 are alternate functions of ALE and WR, respectively. To enable QS0 and QS1, you
must connect the RD pin directly to ground. In this case, RD, WR and ALE are no longer avail-
able and must be generated by external hardware such as an 82C88 or a programmable logic de-
vice.
Table 3-7. Queue Status Signal Decoding
QS1 QS0 Queue Status
0 0 No queue operation occurred.
0 1 The first byte of a new instruction was removed from the queue.
1 0 The queue was reinitialized. All prefetch information was flushed; the BIU must begin
prefetching new queue information.
1 1 A subsequent byte of an instruction was removed from the queue. The current instruction
contains multiple opcode bytes or immediate data.