Intel 80C188XL User Manual

Page 403

Advertising
background image

INDEX

Index-6

Polling, 8-1, 8-9
POPA instruction, A-1
Power consumption‚ reducing, 3-28
Power management, 5-10–5-14
Power management modes

and HALT bus cycles, 3-30

Powerdown mode, 7-2
Power-Save mode, 5-11–5-14, 7-2

and DRAM refresh rate, 5-13
and refresh interval, 7-7
control register, 5-12
entering, 5-11
exiting, 5-13
initialization code, 5-13–5-14

Power-Save Register, 5-12
Priority Mask register, 8-17, 8-18, 8-28
Processor control instructions, 2-27
Processor Status Word (PSW), 2-1, 2-7, 2-41

bits defined, 2-7, 2-9
flag storage formats, 2-19
reset status, 2-7

Program transfer instructions, 2-23–2-24

conditional transfers, 2-24, 2-26
interrupts, 2-26
iteration control, 2-25
unconditional transfers, 2-24

PUSH instruction, A-8
PUSHA instruction, A-1

Q

Queue status signals, 3-38

R

RCL instruction, A-10
RCR instruction, A-10
Read bus cycles‚ See Bus cycles
READY

and chip-selects, 6-15
and normally not-ready signal, 3-17–3-18
and normally ready signal, 3-16–3-17
and PCB accesses, 4-4
and wait states, 3-13–3-18
implementation approaches, 3-13
timing concerns, 3-17

Real, defined, 10-7
Real-time clock, code example, 9-17–9-20
Refresh address, 7-4

Refresh Base Address Register (RFBASE), 7-8
Refresh bus cycle‚ See Bus cycles
Refresh Clock Interval Register (RFTIME), 7-7,

7-8

Refresh Control Register (RFCON), 7-9, 7-10
Refresh Control Unit (RCU), 7-1–7-13

and bus hold protocol, 7-12–7-13
and Powerdown mode, 7-2
and Power-Save mode, 7-2, 7-7
block diagram, 7-1
bus latency, 7-7
calculating refresh interval, 7-7
control registers, 7-7–7-10
initialization code, 7-10
operation, 7-2
overview, 7-2–7-4
programming, 7-7–7-11
relationship to BIU, 7-1

Register operands, 2-27
Registers, 2-1

control, 2-1
data, 2-4, 2-5
general, 2-1, 2-4, 2-5
H & L group, 2-4
index, 2-5, 2-13, 2-34
P & I group, 2-4
pointer, 2-1, 2-5, 2-13
pointer and index, 2-4
segment, 2-1, 2-5, 2-11, 2-12
status, 2-1

Relocation Register‚ See PCB Relocation Register
Reset

and bus hold protocol, 5-6
and clock synchronization, 5-6–5-10
cold, 5-7, 5-8
RC circuit for reset input, 5-7
warm, 5-7, 5-9

ROL instruction, A-10
ROR instruction, A-10

S

SAL instruction, A-9
SAR instruction, A-9
SHL instruction, A-9
Short integer, defined, 10-7
Short real, defined, 10-7
SHR instruction, A-9

Advertising
This manual is related to the following products: