Intel 80C188XL - Manual (Page 149)

CLOCK GENERATION AND POWER MANAGEMENT
5-10
Figure 5-8. Clock Synchronization at Reset
5.2 POWER MANAGEMENT
Many VLSI devices available today use dynamic circuitry. A dynamic circuit uses a capacitor
(usually parasitic gate or diffusion capacitance) to store information. The stored charge decays
over time due to leakage currents in the silicon. If the device does not use the stored information
before it decays, the state of the entire device may be lost. Circuits must periodically refresh dy-
namic RAMs, for example, to ensure data retention. Any microprocessor that has a minimum
clock frequency has dynamic logic. On a dynamic microprocessor, if you stop or slow the clock,
the dynamic nodes within it begin discharging. With a long enough delay, the processor is likely
to lose its present state, needing a reset to resume normal operation.
An 80C186 Modular Core microprocessor is fully static. The CPU stores its current state in
flip-flops, not capacitive nodes. The clock signal to both the CPU core and the peripherals can
stop without losing any internal information, provided the design maintains power. When the
clock restarts, the device will execute from its previous state. When the processor is inactive for
significant periods, special power management hardware takes advantage of static operation to
achieve major power savings.
NOTES:
1. Setup of RES to falling X1.
2. RESYNC pulse generated.
3. RESYNC drives CLKOUT high, resynchronizing the clock generator.
4. RESET goes active.
5. RES allowed to go inactive after minimum 4 CLKOUT cycles.
6. RESET goes inactive 1 1/2 CLKOUT cycles after RES sampled inactive.
X1
CLKOUT
RES
RESYNC
(Internal)
RESET
1
4
3
5 2
6
1
2
A1523-0A