Intel 80C188XL - Manual (Page 205)

INTERRUPT CONTROL UNIT
8-10
8.3.6 Edge and Level Triggering
The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “In-
terrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-trig-
gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must
remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge-
detection circuitry. (See the current data sheet for timing requirements.) The edge-detection cir-
cuitry must be reset to enable further interrupts to occur.
A level-triggered interrupt is generated by a valid logic one on the external interrupt pin. The pin
must remain high until after the CPU acknowledges the interrupt. Unlike edge-triggered inter-
rupts, level-triggered interrupts will continue to occur if the pin remains high. A level-triggered
external interrupt pin must go low before the EOI command to prevent another interrupt.
NOTE
When external 8259As are cascaded into the Interrupt Control Unit, INT0 and
INT1 must be programmed for level-triggered interrupts.
8.3.7 Additional Latency and Response Time
The Interrupt Control Unit adds 5 clocks to the interrupt latency of the CPU. Cascade mode adds
13 clocks to the interrupt response time because the CPU must run the interrupt acknowledge bus
cycles. (See Figure 8-3 on page 8-11 and Figure 2-27 on page 2-46.)