Intel 80C188XL - Manual (Page 192)

7-13
REFRESH CONTROL UNIT
Figure 7-9. Regaining Bus Control to Run a DRAM Refresh Bus Cycle
HLDA
CLKOUT
HOLD
NOTES:
1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T
CLHAV
.
2. External bus master terminates use of the bus.
3. HOLD deasserted; greater than THVCL.
4. Hold may be reasserted after one clock.
5. Lines come out of float in order to run DRAM refresh cycle.
1 4 3
AD15:0
DEN
RD, WR,
BHE, S2:0
DT / R,
A19:16
6
5
2
T1 T1 T1 T1 T1 T4 T1
A1534-0A