NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 102)

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User manual Rev. 2 — 1 November 2010 102 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
speed crystal oscillator or the watchdog oscillator selected by the WDCLK bit in the
WDCON register and XTALWD bit in the CLKCON register. (Note that switching of the
clock sources will not take effect immediately - see
Section 15.3 ).
The watchdog asserts the watchdog reset when the watchdog count underflows and the
watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or
WDCON must be followed by a feed sequence for the new values to take effect.
If a watchdog reset occurs, its behavior is similar to power on reset. Both POF and BOF
are cleared.
15.2 Feed sequence
The watchdog timer control register and the 8-bit down counter (See Figure 50 ) are not
directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end
of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control
register and the 8-bit down counter. Before the feed sequence, any new values written to
these two SFRs will not take effect. To avoid a watchdog reset, the watchdog timer needs
to be fed (via a special sequence of software action called the feed sequence) prior to
reaching an underflow.
Table 96. Watchdog timer configuration
WDTE WDSE FUNCTION
0 x The watchdog reset is disabled. The timer can be used as an internal timer and
can be used to generate an interrupt. WDSE has no effect.
1 0 The watchdog reset is enabled. The user can set WDCLK to choose the clock
source.
1 1 The watchdog reset is enabled, along with additional safety features:
1. WDCLK is forced to 1 (using watchdog oscillator)
2. WDCON and WDL register can only be written once
3. WDRUN is forced to 1
Fig 49. Watchdog Prescaler.
ч2 ч2 ч2 ч2 ч2 ч2 ч2
PRE2
XTALWD
PRE1
PRE0
Watchdog
oscillator
external crystal
oscillator
ч32
ч64 ч32 ч128 ч256 ч512 ч1024 ч2048 ч4096
TO WATCHDOG
DOWN COUNTER
(after one prescaler
count delay)
DECODE
002aae092
000
0
1
001
010
011
100
101
110
111
Watchdog clock
after a Watchdog
feed sequence
0
1
PCLK