NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 66)

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User manual Rev. 2 — 1 November 2010 66 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
10.14 Break detect
A break is detected when 11 consecutive bits are sensed low and is reported in the status
register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit
times. For Modes 2 and 3, this consists of the start bit, 9 data bits, and one stop bit. The
break detect bit is cleared in software or by a reset. The break detect can be used to reset
the device and force the device into ISP mode. This occurs if the UART is enabled and the
the EBRR bit (AUXR1.6) is set and a break occurs.
10.15 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
provided the next character is written between the start bit and the stop bit of the previous
character.
Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out.
10.16 Double buffering in different modes
Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double
buffering must be disabled (DBMOD = 0).
10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)
Unlike the conventional UART, when double buffering is enabled, the Tx interrupt is
generated when the double buffer is ready to receive new data. The following occurs
during a transmission (assuming eight data bits):
1. The double buffer is empty initially.
2. The CPU writes to SBUF.
3. The SBUF data is loaded to the shift register and a Tx interrupt is generated
immediately.
4. If there is more data, go to 6, else continue.
5. If there is no more data, then:
– If DBISEL is logic 0, no more interrupts will occur.
Table 60. FE and RI when SM2 = 1 in Modes 2 and 3
Mode PCON.6
(SMOD0) RB8 RI FE
2 0 0 No RI when RB8 = 0 Occurs during STOP
bit
1 Similar to Figure 29 , with SMOD0 = 0, RI
occurs during RB8, one bit before FE
Occurs during STOP
bit
3 1 0 No RI when RB8 = 0 Will NOT occur
1 Similar to Figure 29 , with SMOD0 = 1, RI
occurs during STOP bit
Occurs during STOP
bit