NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 35)

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User manual Rev. 2 — 1 November 2010 35 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Table 17. Power reduction modes
PMOD1
(PCON.1) PMOD0
(PCON.0) Description
0 0 Normal mode (default) - no power reduction.
0 1 Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the
processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
1 0 Power-down mode:
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC9321 exits Power-down mode via any reset, or certain interrupts - external pins
INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and
comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and
waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit
(IEN0.7) is set. External interrupts should be programmed to level-triggered mode to be used to exit
Power-down mode.
In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been
selected as the system clock AND the RTC is enabled.
In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage
VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after V
DD
has been lowered to VRAM, therefore it is recommended to
wake-up the processor via Reset in this situation. V
DD
must be raised to within the operating range
before the Power-down mode is exited.
When the processor wakes up from Power-down mode, it will start the oscillator immediately and
begin execution when the oscillator is stable. Oscillator stability is determined by counting 1024
CPU clocks after start-up when one of the crystal oscillator configurations is used, or 200ms to
300ms after start-up for the internal RC, or 32 OSCCLK cycles after start-up for external clock input.
Some chip functions continue to operate and draw power during Power-down mode, increasing the
total power used during power-down. These include:
• Brownout Detect
• Watchdog Timer if WDCLK (WDCON.0) is logic 1.
• Comparators (Note: Comparators can be powered down separately with PCONA.5 set to
logic 1 and comparators disabled);
• Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless
RTCPD, i.e., PCONA.7 is logic 1).
1 1 Total Power-down mode: This is the same as Power-down mode except that the Brownout
Detection circuitry and the voltage comparators are also disabled to conserve additional power.
Note that a brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout
interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both
the RC oscillator has been selected as the system clock AND the RTC is enabled.
The following are the wake-up options supported:
• Watchdog Timer if WDCLK (WDCON.0) is logic 1. Could generate Interrupt or Reset, either
one can wake up the device
• External interrupts INTO/INT1 (when programmed to level-triggered mode).
•
Keyboard Interrupt
•
Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless
RTCPD, i.e., PCONA.7 is logic 1).
Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively
high power consumption. Lower power consumption can be achieved by using an external low
frequency clock when the Real-time Clock or watchdog timer is running during power-down.