NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 59)

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User manual Rev. 2 — 1 November 2010 59 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
10. UART
The P89LPC9321 has an enhanced UART that is compatible with the conventional 80C51
UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC9321 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, break detect, automatic address
recognition, selectable double buffering and several interrupt options.
The UART can be operated in 4 modes, as described in the following sections.
10.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1 ⁄
16
of the CPU clock
frequency.
10.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in
RB8 in Special Function Register SCON. The baud rate is variable and is determined by
the Timer 1 overflow rate or the Baud Rate Generator (see
Section 10.6 “Baud Rate
generator and selection” ).
10.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for
example, the parity bit (P, in the PSW) could be moved into TB8. When data is received,
the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not
saved. The baud rate is programmable to either
1 ⁄
16
or 1 ⁄
32
of the CCLK frequency, as
determined by the SMOD1 bit in PCON.
5 TOCIE2C Output Compare Channel C Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel
C is enabled and the contents of TH2:TL2 match that of OCRHC:OCRLC, the program counter will
vectored to the corresponding interrupt.
6 TOCIE2D Output Compare Channel D Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel
D is enabled and the contents of TH2:TL2 match that of OCRHD:OCRLD, the program counter will
vectored to the corresponding interrupt.
7 TOIE2 CCU Timer Overflow Interrupt Enable bit.
Table 50. CCU interrupt control register (TICR2 - address C9h) bit description …continued
Bit Symbol Description