NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 64)

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User manual Rev. 2 — 1 November 2010 64 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
10.11 More about UART Mode 1
Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampled at a rate 16
times the programmed baud rate. When a transition is detected, the divide-by-16 counter
is immediately reset. Each bit time is thus divided into 16 counter states. At the 7th, 8th,
and 9th counter states, the bit detector samples the value of RxD. The value accepted is
the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If
the value accepted during the first bit time is not 0, the receive circuits are reset and the
receiver goes back to looking for another 1-to-0 transition. This provides rejection of false
start bits. If the start bit proves valid, it is shifted into the input shift register, and reception
of the rest of the frame will proceed.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated: RI = 0 and either
SM2 = 0 or the received stop bit = 1. If either of these two conditions is not met, the
received frame is lost. If both conditions are met, the stop bit goes into RB8, the 8 data
bits go into SBUF, and RI is activated.
Fig 27. Serial Port Mode 0 (double buffering must be disabled)
002aaa925
transmit
RXD (data out)
RXD
(data in)
D0 D1 D5 D2 D6 D3 D4 D7
TXD (shift clock)
shift
S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16
write to
SBUF
TI
receive
D0 D1 D5 D2 D6 D3 D4 D7
TXD (shift clock)
shift
WRITE to SCON
(clear RI)
RI