NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 111)

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User manual Rev. 2 — 1 November 2010 111 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data
EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF
is logic 1, the operation is complete and data is written.
6. Poll EWERR0 flag. If EWERR0 (DEECON.1) bit is logic 1, it means BOD EEPROM
occurred (V
DD
<2.4V) during program or erase and the previous operation may not be
correct.
As a write to the DEEDAT register followed by a write to the DEEADR register will
automatically set off a write (if DEECON[5:4] = ‘00’), the user must take great caution in a
write to the DEEDAT register. It is strongly recommended that the user disables interrupts
prior to a write to the DEEDAT register and enable interrupts after all writes are over. An
example is as follows:
CLR EA ;disable interrupt
MOV DEEDAT,@R0 ;write data pattern
MOV DEEADR,@R1 ;write address for the data
SETB EA ;wait for the interrupt orpoll the DEECON.7 (EEIF) bit
17.3 Hardware reset
During any hardware reset, including watchdog and system timer reset, the state machine
that ‘remembers’ a write to the DEEDAT register will be initialized. If a write to the
DEEDAT register occurs followed by a hardware reset, a write to the DEEADR register
without a prior write to the DEEDAT register will result in a read cycle.
17.4 Multiple writes to the DEEDAT register
If there are multiple writes to the DEEDAT register before a write to the DEEADR register,
the last data written to the DEEDAT register will be written to the corresponding address.
17.5 Sequences of writes to DEECON and DEEDAT registers
A write to the DEEDAT register is considered a valid write (i.e, will trigger the state
machine to ‘remember’ a write operation is to commence) if DEECON[5:4] = ‘00’. If these
mode bits are already ‘00’ and address bit 8 is correct, there is no need to write to the
DEECON register prior to a write to the DEEDAT register.
17.6 Data EEPROM Row Fill
A row (64 bytes) can be filled with a predetermined data pattern via polling or interrupt:
1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘10’ and EWERR1/EWERR0
(DEECON[2:1]) =’00’ and correct bit 8 address to EADR8. (Note that if the correct
values are already written to DEECON, there is no need to write to this register.)
2. Write the fill pattern to the DEEDAT register. (Note that if the correct values are
already written to DEEDAT, there is no need to write to this register.)
3. Write address bits 7 to 0 to DEEADR. Note that address bits 5 to 0 are ignored.
4. Poll EWERR1 flag. If EWERR1 (DEECON.2) bit is logic 1, BOD EEPROM occurred
(V
DD
<2.4V) and Data EEPROM program is blocked.