NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 42)

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User manual Rev. 2 — 1 November 2010 42 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware
when the interrupt is processed, or by software.
4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)
6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off
7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt
is processed, or by software (except in mode 6, see above, when it is cleared in hardware).
Table 29. Timer/Counter Control register (TCON - address 88h) bit description …continued
Bit Symbol Description
Fig 15. Timer/counter 0 or 1 in Mode 0 (13-bit counter).
002aaa919
PCLK
Tn pin
TRn
Gate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt
Fig 16. Timer/counter 0 or 1 in mode 1 (16-bit counter).
002aaa920
PCLK
Tn pin
TRn
Gate
INTn pin
C/T = 0
C/T = 1
TLn
(8-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt
Fig 17. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload).
002aaa921
PCLK
Tn pin
TRn
Gate
INTn pin
C/T = 0
C/T = 1
TLn
(8-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt
reload