NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 9)

UM10310 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 1 November 2010 9 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
1.4 Block diagram
Fig 5. Block diagram
ACCELERATED 2-CLOCK 80C51 CPU
8 kB
CODE FLASH
256-BYTE
DATA RAM
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
CONFIGURABLE
OSCILLATOR
ON-CHIP RC
OSCILLATOR
WITH CLOCK
DOUBLER
internal bus
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aae102
UART
ANALOG
COMPARATORS
512-BYTE
AUXILIARY RAM
I 2 C-BUS
512-BYTE
DATA EEPROM
PORT 3
CONFIGURABLE I/Os
CCU (CAPTURE/
COMPARE UNIT)
P89LPC9321
WATCHDOG TIMER
AND OSCILLATOR
TIMER 0
TIMER 1
REAL-TIME CLOCK/
SYSTEM TIMER
SPI
P3[1:0]
P2[7:0]
P1[7:0]
P0[7:0]
TXD
RXD
SCL
SDA
T0
T1
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
OCA
OCB
OCC
OCD
ICA
ICB
SPICLK
MOSI
MISO
SS
CRYSTAL
OR
RESONATOR
XTAL2
XTAL1