NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 50)

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User manual Rev. 2 — 1 November 2010 50 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
9.4 Output compare
The four output compare channels A, B, C and D are controlled through four 16-bit SFRs,
OCRAH:OCRAL, OCRBH:OCRBL, OCRCH:OCRCL, OCRDH: OCRDL. Each output
compare channel needs to be enabled in order to operate. The channel is enabled by
selecting a Compare Output Action by setting the OCMx1:0 bits in the Capture Compare x
Control Register - CCCRx (x = A, B, C, D). When a compare channel is enabled, the user
will have to set the associated I/O pin to the desired output mode to connect the pin.
(Note: The SFR bits for port pins P2.6, P1.6, P1.7, P2.1 must be set to logic 1 in order for
the compare channel outputs to be visible at the port pins.) When the contents of TH2:TL2
match that of OCRxH:OCRxL, the Timer Output Compare Interrupt Flag - TOCFx is set in
TIFR2. This happens in the CCUCLK cycle after the compare takes place. If EA and the
Timer Output Compare Interrupt Enable bit - TOCIE2x (in TICR2 register), as well as
ECCU bit in IEN1 are all set, the program counter will be vectored to the corresponding
interrupt. The user must manually clear the bit by writing a logic 0 to it.
5 TPCR2L.5 Prescaler bit 5
6 TPCR2L.6 Prescaler bit 6
7 TPCR2L.7 Prescaler bit 7
Table 36. CCU prescaler control register, low byte (TPCR2L - address CAh) bit description
Bit Symbol Description
Table 37. CCU control register 0 (TCR20 - address C8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20
Reset 0 0 0 0 0 0 0 0
Table 38. CCU control register 0 (TCR20 - address C8h) bit description
Bit Symbol Description
1:2 TMOD20/21 CCU Timer mode (TMOD21, TMOD20):
00 — Timer is stopped
01 — Basic timer function
10 — Asymmetrical PWM (uses PLL as clock source)
11 — Symmetrical PWM (uses PLL as clock source)
2 TDIR2 Count direction of the CCU Timer. When logic 0, count up, When logic 1, count down.
3 ALTAB PWM channel A/B alternately output enable. When this bit is set, the output of PWM channel A and B
are alternately gated on every counter cycle.
4 ALTCD PWM channel C/D alternately output enable. When this bit is set, the output of PWM channel C and D
are alternately gated on every counter cycle.
5 HLTEN PWM Halt Enable. When logic 1, a capture event as enabled for Input Capture A pin will immediately
stop all activity on the PWM pins and set them to a predetermined state.
6 HLTRN PWM Halt. When set indicates a halt took place. In order to re-activate the PWM, the user must clear
the HLTRN bit.
7 PLLEN Phase Locked Loop Enable. When set to logic 1, starts PLL operation. After the PLL is in lock this bit it
will read back a one.