NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 49)

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User manual Rev. 2 — 1 November 2010 49 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
depends on whether the timer is running in PWM mode or in basic timer mode. In basic
timer mode, writing a one to TCOU2 will cause the values to be latched immediately and
the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will
cause the contents of the shadow registers to be updated on the next CCU Timer
overflow. As long as the latch is pending, TCOU2 will read as one and will return to zero
when the latching takes place. TCOU2 also controls the latching of the Output Compare
registers OCR2A, OCR2B and OCR2C.
When writing to timer high byte, TH2, the value written is stored in a shadow register.
When TL2 is written, the contents of TH2’s shadow register is transferred to TH2 at the
same time that TL2 gets updated. Thus, TH2 should be written prior to writing to TL2. If a
write to TL2 is followed by another write to TL2, without TH2 being written in between, the
value of TH2 will be transferred directly to the high byte of the timer.
If the 16-bit CCU Timer is to be used as an 8-bit timer, the user can write FFh (for
upcounting) or 00h (for downcounting) to TH2. When TL2 is written, FFh:TH2 (for
upcounting) and 00h (for downcounting) will be loaded to CCU Timer. The user will not
need to rewrite TH2 again for an 8-bit timer operation unless there is a change in count
direction
When reading the timer, TL2 must be read first. When TL2 is read, the contents of the
timer high byte are transferred to a shadow register in the same PCLK cycle as the read is
performed. When TH2 is read, the contents of the shadow register are read instead. If a
read from TL2 is followed by another read from TL2 without TH2 being read in between,
the high byte of the timer will be transferred directly to TH2.
Table 33. CCU prescaler control register, high byte (TPCR2H - address CBh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol - - - - - - TPCR2H.1 TPCR2H.0
Reset x x x x x x 0 0
Table 34. CCU prescaler control register, high byte (TPCR2H - address CBh) bit description
Bit Symbol Description
0 TPCR2H.0 Prescaler bit 8
1 TPCR2H.1 Prescaler bit 9
Table 35. CCU prescaler control register, low byte (TPCR2L - address CAh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0
Reset 0 0 0 0 0 0 0 0
Table 36. CCU prescaler control register, low byte (TPCR2L - address CAh) bit description
Bit Symbol Description
0 TPCR2L.0 Prescaler bit 0
1 TPCR2L.1 Prescaler bit 1
2 TPCR2L.2 Prescaler bit 2
3 TPCR2L.3 Prescaler bit 3
4 TPCR2L.4 Prescaler bit 4