7 alternating output mode, 8 synchronized pwm register update, Table 42 “output compare pin behavior – NXP Semiconductors P89LPC9321 UM10310 User Manual

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User manual

Rev. 2 — 1 November 2010

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NXP Semiconductors

UM10310

P89LPC9321 User manual

9.7 Alternating

output

mode

In asymmetrical mode, the user can program PWM channels A/B and C/D as alternating
pairs for bridge drive control. By setting ALTAB or ALTCD bits in TCR20, the output of
these PWM channels are alternately gated on every counter cycle. This is shown in the
following figure:

[1]

x = A, B, C, D

[2]

‘ON’ means in the CCUCLK cycle after the event takes place.

9.8 Synchronized PWM register update

When the OCRx registers are written, a built in mechanism ensures that the value is not
updated in the middle of a PWM pulse. This could result in an odd-length pulse. When the
registers are written, the values are placed in two shadow registers, as is the case in basic
timer operation mode. Writing to TCOU2 will cause the contents of the shadow registers
to be updated on the next CCU Timer overflow. If OCRxH and/or OCRxL are read before
the value is updated, the most currently written value is read.

Fig 24. Alternate output mode.

Table 42.

Output compare pin behavior.

OCMx1

[1]

OCMx0

[1]

Output Compare pin behavior

Basic timer mode

Asymmetrical PWM

Symmetrical PWM

Output compare disabled. On power-on, this is the default state, and pins
are configured as inputs.