NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 107)

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User manual Rev. 2 — 1 November 2010 107 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
15.5 Power-down operation
The WDT oscillator and low speed crystal oscillator will continue to run in power-down,
consuming approximately 50
μA, as long as the WDT oscillator is selected as the clock
source for the WDT. Selecting PCLK as the WDT source will result in the WDT oscillator
going into power-down with the rest of the device (see
Section 15.3 ). Power-down mode
will also prevent PCLK from running and therefore the watchdog is effectively disabled.
15.6 Periodic wake-up from power-down without an external oscillator
Without using an external oscillator source, the power consumption required in order to
have a periodic wake-up is determined by the power consumption of the internal oscillator
source used to produce the wake-up. The Real-time clock running from the internal RC
oscillator can be used. The power consumption of this oscillator is approximately 300
μA.
Instead, if the WDT is used to generate interrupts the current is reduced to approximately
50
μA. Whenever the WDT underflows, the device will wake-up.
16. Additional features
The AUXR1 register contains several special purpose control bits that relate to several
chip features. AUXR1 is described in
Table 102
Fig 51. Watchdog Timer in Timer Mode (WDTE = 0).
PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aae094
8-BIT DOWN
COUNTER
WDL (C1H)
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset Watchdog
oscillator
external
crystal
oscillator
0
1
0
1
PCLK
XTALWD
Table 101. AUXR1 register (address A2h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CLKLP EBRR ENT1 ENT0 SRST 0 - DPS
Reset 0 0 0 0 0 0 x 0