NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 22)

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User manual Rev. 2 — 1 November 2010 22 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
2.3.2 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
2.3.3 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
2.4 Clock output
The P89LPC9321 supports a user-selectable clock output function on the XTAL2 /
CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a
different clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the Real-time Clock and Watchdog Timer are not using
the crystal oscillator as their clock source. This allows external devices to synchronize to
the P89LPC9321. This output is enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is 1 ⁄
2
that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on
reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when
setting or clearing the ENCLK bit, the user should retain the contents of other bits of the
TRIM register. This can be done by reading the contents of the TRIM register (into the
ACC for example), modifying bit 6, and writing this result back into the TRIM register.
Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6
of the TRIM register.
2.5 On-chip RC oscillator option
The P89LPC9321 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed
value to adjust the oscillator frequency to 7.373 MHz
± 1 % at room temperature. (Note:
the initial value is better than 1 %; please refer to the P89LPC9321 data sheet for
behavior over temperature). End user applications can write to the TRIM register to adjust
the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease
the oscillator frequency. When the clock doubler option is enabled (UCFG2.7 = 1), the
output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7)
can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing
highest performance access. This bit can then be set in software if CCLK is running at
8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0
bit (UCFG1.3) are required to hold the device in reset at power-up until V
DD
has reached
its specified level.
Table 5. On-chip RC oscillator trim register (TRIM - address 96h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
Reset 0 0 Bits 5:0 loaded with factory stored value during reset.