NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 37)

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User manual Rev. 2 — 1 November 2010 37 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
6. Reset
The P1.5/RST pin can function as either an active low reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset
input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-on sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not hold
this pin low during a Power-on sequence as this will keep the device in reset. After
power-on this input will function either as an external reset input or as a digital input as
defined by the RPE bit. Only a power-on reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Note: During a power cycle, V
DD
must fall below V
POR
(see P89LPC9321 data sheet,
Static characteristics) before power is reapplied, in order to ensure a power-on reset.
Reset can be triggered from the following sources:
• External reset pin (during power-on or if user configured via UCFG1);
• Power-on detect;
• Brownout detect;
• Watchdog timer;
• Software reset;
• UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• A watchdog reset is similar to a power-on reset, both POF and BOF are set but the
other flag bits are cleared.
• For any other reset, previously set flag bits that have not been cleared will remain set.
5 VCPD Analog Voltage Comparators power-down: When logic 1, the voltage comparators
are powered down. User must disable the voltage comparators prior to setting this
bit.
6 DEEPD Data EEPROM power-down: When logic 1, the Data EEPROM is powered down.
Note that in either Power-down mode or Total Power-down mode, the Data
EEPROM will be powered down regardless of this bit.
7 RTCPD Real-time Clock power-down: When logic 1, the internal clock to the Real-time
Clock is disabled.
Table 21. Power Control register A (PCONA - address B5h) bit description …continued
Bit Symbol Description