NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 136)

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User manual Rev. 2 — 1 November 2010 136 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Table 68. I 2 C Status register (I2STAT - address D9h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 69. I 2 C Status register (I2STAT - address D9h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 70. I 2 C clock rates selection . . . . . . . . . . . . . . . . .74
Table 71. I 2 C Control register (I2CON - address D8h) . .74
Table 72. I 2 C Control register (I2CON - address D8h) . .76
Table 73. Master Transmitter mode . . . . . . . . . . . . . . . . .79
Table 74. Master Receiver mode . . . . . . . . . . . . . . . . . .80
Table 75. Slave Receiver mode . . . . . . . . . . . . . . . . . . .81
Table 76. Slave Transmitter mode . . . . . . . . . . . . . . . . . .83
Table 77. SPI Control register (SPCTL - address E2h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 78. SPI Control register (SPCTL - address E2h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 79. SPI Status register (SPSTAT - address E1h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 80. SPI Status register (SPSTAT - address E1h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 81. SPI Data register (SPDAT - address E3h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 82. SPI master and slave selection . . . . . . . . . . . .88
Table 83. Comparator Control register (CMP1 - address
ACh, CMP2 - address ADh) bit allocation . . . .95
Table 84. Comparator Control register (CMP1 - address
ACh, CMP2 - address ADh) bit description . . .95
Table 85. PGA trim register . . . . . . . . . . . . . . . . . . . . . .99
Table 86. PGA1 Control register (PGACON1 - address
FFE1h) bit allocation . . . . . . . . . . . . . . . . . . . .99
Table 87. PGA1 Control register (PGACON1 - address
FFE1h) bit description . . . . . . . . . . . . . . . . . . .99
Table 88. PGA1 Control register B (PGACON1B - address
FFE4h) bit allocation . . . . . . . . . . . . . . . . . . . .99
Table 89. PGA1 Control register B (PGACON1B - address
FFE4h) bit description . . . . . . . . . . . . . . . . . . .99
Table 90. Keypad Pattern register (KBPATN - address 93h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 91. Keypad Pattern register (KBPATN - address 93h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .100
Table 92. Keypad Control register (KBCON - address 94h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 93. Keypad Control register (KBCON - address 94h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .100
Table 94. Keypad Interrupt Mask register (KBMASK -
address 86h) bit allocation . . . . . . . . . . . . . . .101
Table 95. Keypad Interrupt Mask register (KBMASK -
address 86h) bit description . . . . . . . . . . . . .101
Table 96. Watchdog timer configuration . . . . . . . . . . . .102
Table 97. Watchdog Timer Control register (WDCON -
address A7h) bit allocation . . . . . . . . . . . . . .104
Table 98. Watchdog Timer Control register (WDCON -
address A7h) bit description . . . . . . . . . . . . .104
Table 99. Watchdog timeout vales . . . . . . . . . . . . . . . .104
Table 100. Watchdog input clock selection . . . . . . . . . . .105
Table 101. AUXR1 register (address A2h) bit allocation 107
Table 102. AUXR1 register (address A2h) bit description . .
108
Table 103. Data EEPROM control register (DEECON
address F1h) bit allocation. . . . . . . . . . . . . . . 109
Table 104. Data EEPROM control register (DEECON
address F1h) bit description. . . . . . . . . . . . . . 109
Table 105. Flash Memory Control register (FMCON -
address E4h) bit allocation . . . . . . . . . . . . . . 115
Table 106. Flash Memory Control register (FMCON -
address E4h) bit description . . . . . . . . . . . . . 115
Table 107. Boot loader address and default Boot vector 118
Table 108. In-system Programming (ISP) hex record
formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 109. IAP error status . . . . . . . . . . . . . . . . . . . . . . 124
Table 110. IAP function calls . . . . . . . . . . . . . . . . . . . . . 125
Table 111. Flash User Configuration Byte 1 (UCFG1) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 112. Flash User Configuration Byte 1 (UCFG1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 113. Oscillator type selection . . . . . . . . . . . . . . . . 128
Table 114. Flash User Configuration Byte 2 (UCFG2) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 115. Flash User Configuration Byte 2 (UCFG2) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 116. Sector Security Bytes (SECx) bit allocation . 128
Table 117. Sector Security Bytes (SECx) bit description 129
Table 118. Effects of Security Bits . . . . . . . . . . . . . . . . . 129
Table 119. Boot Vector (BOOTVEC) bit allocation . . . . . 129
Table 120. Boot Vector (BOOTVEC) bit description . . . 129
Table 121. Boot Status (BOOTSTAT) bit allocation . . . . 129
Table 122. Boot Status (BOOTSTAT) bit description . . . 130
Table 123. Instruction set summary . . . . . . . . . . . . . . . . 131