NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 98)

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User manual Rev. 2 — 1 November 2010 98 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
;Positive input on CIN1A.
;Negative input from CMPREF pin.
;Output to CMP1 pin enabled.
CALL delay10us ;The comparator needs at least 10 microseconds
before use.
ANL CMP1,#0FEh ;Clear comparator 1 interrupt flag.
SETB EC ;Enable the comparator interrupt,
SETB EA ;Enable the interrupt system (if needed).
RET ;Return to caller.
The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this
case) before returning.
13.7 Programmable Gain Amplifier (PGA)
PGA1 is integrated to amplify the comparators inputs. A single channel can be selected
for amplification. The block diagram of PGA1 is shown in
Figure 48 .
Register PGACON1 and PGACON1B are used for PGA1 configuration. The gain of PGA1
can be programmable to 2, 4, 8 or 16 by configuring PGAG11 and PGAG10 bits. PGA is
enabled by setting ENPGA1 bit. If ENPGA1 is cleared, PGA1 is disabled and bypassed,
which means the PGA1 gain value is 1.
Four external input signals are selected by configuring PGASEL11 and PGASEL10 bits.
PGA offset voltage is used to guarantee the linearity of PGA output. When enable
PGAENOFFx bit in register PGACONxB, PGA output will be the PGA input plus offset
voltage. PGA input can be grounded by setting PGATRIMx bit.
4-bit trim value is used to provide the PGA offset voltage in PGA trim registers
PGAxTRIM2X4X and PGAxTRIM8X16X. End users application can write to PGA trim
registers to adjust PGA offset voltage. Increasing 4-bit trim value will increase the
corresponding PGA offset voltage. During reset, 4-bits trim value is initialized to a factory
pre-programmed value. To guarantee the linearity of PGA output, it is recommended not
to change the PGA trim registers.
Fig 48. PGA1 block diagram
002aae212
CIN2B
CIN2A
CIN1B
CIN1A
PGA1 TRIM
REGISTERS
MUX
MUX
4
Σ
PGASEL11,
PGASEL10
PGA11, PGA10
PGA1 GAIN
PGATRIM1