NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 53)

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User manual Rev. 2 — 1 November 2010 53 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
In symmetrical mode, the timer counts up/down alternately and the value of TDIR2 has no
effect. The main difference from basic timer operation is the operation of the compare
module, which in PWM mode is used for PWM waveform generation.
Table 42 shows the
behavior of the compare pins in PWM mode.
The user will have to configure the output compare pins as outputs in order to enable the
PWM output. As with basic timer operation, when the PWM (compare) pins are connected
to the compare logic, their logic state remains unchanged. However, since the bit FCO is
used to hold the halt value, only a compare event can change the state of the pin.
The CCU Timer Overflow interrupt flag is set when the counter changes direction at the
top. For example, if TOR contains 01FFH, CCU Timer will count: …01FEH, 01FFH,
01FEH,… The flag is set in the counter cycle after the change from TOR to TOR-1.
When the timer changes direction at the bottom, in this example, it counts …,0001H,
0000H, 0001H,… The CCU Timer overflow interrupt flag is set in the counter CCUCLK
cycle after the transition from 0001H to 0000H.
The status of the TDIR2 bit in TCR20 reflects the current counting direction. Writing to this
bit while operating in symmetrical mode has no effect.
Fig 22. Asymmetrical PWM, downcounting.
Fig 23. Symmetrical PWM.
TOR2
compare value
timer value
non-inverted
inverted
0x0000
002aaa893
TOR2
compare value
timer value
non-inverted
inverted
002aaa894
0