NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 139)

NXP Semiconductors
UM10310
P89LPC9321 User manual
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 1 November 2010
Document identifier: UM10310
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11.3 I 2 C control register . . . . . . . . . . . . . . . . . . . . . 72
11.4 I 2 C Status register. . . . . . . . . . . . . . . . . . . . . . 73
11.5 I 2 C SCL duty cycle registers I2SCLH and I2SCLL
73
11.6 I 2 C operation modes. . . . . . . . . . . . . . . . . . . . 74
11.6.1 Master Transmitter mode . . . . . . . . . . . . . . . . 74
11.6.2 Master Receiver mode . . . . . . . . . . . . . . . . . . 75
11.6.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . . 76
11.6.4 Slave Transmitter mode . . . . . . . . . . . . . . . . . 77
12 Serial Peripheral Interface (SPI) . . . . . . . . . . . 84
12.1 Configuring the SPI . . . . . . . . . . . . . . . . . . . . 88
12.2 Additional considerations for a slave . . . . . . . 89
12.3 Additional considerations for a master . . . . . . 89
12.4 Mode change on SS . . . . . . . . . . . . . . . . . . . . 89
12.5 Write collision . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.6 Data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.7 SPI clock prescaler select . . . . . . . . . . . . . . . 94
13 Analog comparators . . . . . . . . . . . . . . . . . . . . 94
13.1 Comparator configuration . . . . . . . . . . . . . . . . 94
13.2 Internal reference voltage . . . . . . . . . . . . . . . . 96
13.3 Comparator input pins . . . . . . . . . . . . . . . . . . 96
13.4 Comparator interrupt. . . . . . . . . . . . . . . . . . . . 96
13.5 Comparators and power reduction modes . . . 97
13.6 Comparators configuration example. . . . . . . . 97
13.7 Programmable Gain Amplifier (PGA) . . . . . . . 98
14 Keypad interrupt (KBI). . . . . . . . . . . . . . . . . . 100
15 Watchdog timer (WDT) . . . . . . . . . . . . . . . . . 101
15.1 Watchdog function . . . . . . . . . . . . . . . . . . . . 101
15.2 Feed sequence . . . . . . . . . . . . . . . . . . . . . . . 102
15.3 Watchdog clock source . . . . . . . . . . . . . . . . 105
15.4 Watchdog Timer in Timer mode . . . . . . . . . . 106
15.5 Power-down operation . . . . . . . . . . . . . . . . . 107
15.6 Periodic wake-up from power-down without an
external oscillator . . . . . . . . . . . . . . . . . . . . . 107
16 Additional features . . . . . . . . . . . . . . . . . . . . 107
16.1 Software reset. . . . . . . . . . . . . . . . . . . . . . . . 108
16.2 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . 108
17 Data EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . 109
17.1 Data EEPROM read . . . . . . . . . . . . . . . . . . . 110
17.2 Data EEPROM write . . . . . . . . . . . . . . . . . . . 110
17.3 Hardware reset . . . . . . . . . . . . . . . . . . . . . . . 111
17.4 Multiple writes to the DEEDAT register. . . . . 111
17.5 Sequences of writes to DEECON and DEEDAT
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
17.6 Data EEPROM Row Fill . . . . . . . . . . . . . . . . 111
17.7 Data EEPROM Block Fill . . . . . . . . . . . . . . . 112
18 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 112
18.1 General description . . . . . . . . . . . . . . . . . . . 112
18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
18.3 Flash programming and erase . . . . . . . . . . . . 113
18.4 Using Flash as data storage: IAP-Lite . . . . . . 113
18.5 In-circuit programming (ICP) . . . . . . . . . . . . . 117
18.6 ISP and IAP capabilities of the P89LPC9321 117
18.7 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
18.8 Power on reset code execution . . . . . . . . . . . 117
18.9 Hardware activation of Boot Loader. . . . . . . . 118
18.10 In-system programming (ISP) . . . . . . . . . . . . 118
18.11 Using the In-system programming (ISP) . . . . 119
18.12 In-application programming (IAP) . . . . . . . . 122
18.13 IAP authorization key . . . . . . . . . . . . . . . . . . 122
18.14 Flash write enable . . . . . . . . . . . . . . . . . . . . 122
18.15 Configuration byte protection . . . . . . . . . . . . 123
18.16 IAP error status . . . . . . . . . . . . . . . . . . . . . . 123
18.17 User configuration bytes . . . . . . . . . . . . . . . 127
18.18 User security bytes . . . . . . . . . . . . . . . . . . . 128
18.19 Boot Vector register . . . . . . . . . . . . . . . . . . . 129
18.20 Boot status register . . . . . . . . . . . . . . . . . . . 129
19 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . 131
20 Legal information . . . . . . . . . . . . . . . . . . . . . 134
20.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 134
20.2 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 134
20.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 134
21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
23 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138