NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 43)

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User manual Rev. 2 — 1 November 2010 43 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
7.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs and
PWM outputs are also used for the timer toggle outputs. This function is enabled by
control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1
respectively. The port outputs will be a logic 1 prior to the first timer overflow when this
mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting
PCLK as the clock source for the timer.
8. Real-time clock system timer
The P89LPC9321 has a simple Real-time Clock/System Timer that allows a user to
continue running an accurate timer while the rest of the device is powered down. The
Real-time Clock can be an interrupt or a wake-up source (see
Figure 20 ).
Fig 18. Timer/counter 0 Mode 3 (two 8-bit counters).
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PCLK
Osc/2
T0 pin
TR0
TR1
Gate
INT0 pin
C/T = 0
C/T = 1
TL0
(8-bits)
TF0
control
ENT0
(AUXR1.4)
T0 pin
(P1.2 open drain)
toggle
overflow
interrupt
TH0
(8-bits)
TF1
control
ENT1
(AUXR1.5)
T1 pin
(P0.7)
toggle
overflow
interrupt
Fig 19. Timer/counter 0 or 1 in mode 6 (PWM auto-reload).
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PCLK
TRn
Gate
INTn pin
C/T = 0
TLn
(8-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt
reload THn on falling transition
and (256-THn) on rising transition