NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 15)

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UM10
310
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Rev
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15 of
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UM10310
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P1* Port 1 90H OCC OCB RST INT1 INT0/SDA T0/SCL RXD TXD [1]
Bit address A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2 A0H ICA OCA SPICLK SS MISO MOSI OCD ICB [1]
Bit address B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H - - - - - - XTAL1 XTAL2 [1]
P0M1 Port 0 output
mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF [1] 1111 1111
P0M2 Port 0 output
mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 [1] 0000 0000
P1M1 Port 1 output
mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 [1] 11x1 xx11
P1M2 Port 1 output
mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 [1] 00x0 xx00
P2M1 Port 2 output
mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF [1] 1111 1111
P2M2 Port 2 output
mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00 [1] 0000 0000
P3M1 Port 3 output
mode 1 B1H - - - - - - (P3M1.1) (P3M1.0) 03 [1] xxxx xx11
P3M2 Port 3 output
mode 2 B2H - - - - - - (P3M2.1) (P3M2.0) 00 [1] xxxx xx00
PCON Power control
register 87H SMOD1 SMOD0 - BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000
PCONA Power control
register A B5H RTCPD DEEPD VCPD - I2PD SPPD SPD CCUPD 00 [1] 0000 0000
Bit address D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status
word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000
PT0AD Port 0 digital
input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x
RSTSRC Reset source
register DFH - BOIF BOF POF R_BK R_WD R_SF R_EX [3]
RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 [1][6] 011x xx00
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary