NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 94)

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User manual Rev. 2 — 1 November 2010 94 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
12.7 SPI clock prescaler select
The SPI clock prescaler selection uses the SPR1-SPR0 bits in the SPCTL register (see
Table 78 ).
13. Analog comparators
Two analog comparators are provided on the P89LPC9321. Input and output options
allow use of the comparators in a number of different configurations. Comparator
operation is such that the output is a logic 1 (which may be read in a register and/or routed
to a pin) when the positive input (one of two selectable pins) is greater than the negative
input (selectable from a pin or an internal reference voltage). Otherwise the output is a
zero. Each comparator may be configured to cause an interrupt when the output value
changes.
The comparators inputs can be amplified by using PGA1 module. The PGA1 can supply
gain factors of 2x, 4x, 8x, or 16x, eliminating the need for external opamps in the end
application. Refer to
Section 13.7 “Programmable Gain Amplifier (PGA)” for PGA details.
13.1 Comparator configuration
Each comparator has a control register, CMP1 for comparator 1 and CMP2 for comparator
2. The control registers are identical and are shown in
Table 84 .
(1) Not defined
Fig 45. SPI master transfer format with CPHA = 1.
1 2 3 4 5 6 7 8
MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
LSB
MSB
MSB
LSB
DORD = 0
DORD = 1
6
1
5
2
4
3
3
4
2
5
1
6
LSB
MSB
002aaa937
Clock cycle
SPICLK (CPOL = 0)
SPICLK (CPOL = 1)
MOSI (input)
MISO (output)
SS (if SSIG bit = 0)
DORD = 0
DORD = 1