NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 28)

UM10310 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 1 November 2010 28 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
4. I/O ports
The P89LPC9321 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1,and 2
are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends
upon the clock and reset options chosen (see
Table 12 ).
Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources.
002aae160
IE0
EX0
IE1
EX1
BOIF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
SI
EI2C
SPIF
ESPI
RTCF
ERTC
(RTCCON.1)
WDOVF
TF0
ET0
any CCU interrupt
ECCU
EEIF
EIEE
Table 12. Number of I/O pins available
Clock source Reset option Number of I/O
pins
On-chip oscillator or watchdog
oscillator No external reset (except during power up) 26
External RST pin supported 25
External clock input No external reset (except during power up) 25
External RST pin supported 24
Low/medium/high speed oscillator
(external crystal or resonator) No external reset (except during power up) 24
External RST pin supported 23