Nxp semiconductors – NXP Semiconductors P89LPC9321 UM10310 User Manual
Page 104
UM10310
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User manual
Rev. 2 — 1 November 2010
104 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
(3)
shows sample P89LPC9321 timeout values.
tclks
2
5
7
+
(
)
(
) 255 1
+
(
) 1 1048577
=
+
=
Table 97.
Watchdog Timer Control register (WDCON - address A7h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
Reset
1
1
1
x
x
1
1/0
1
Table 98.
Watchdog Timer Control register (WDCON - address A7h) bit description
Bit Symbol
Description
0
WDCLK
Watchdog input clock select. When set, the watchdog oscillator is selected. When cleared, PCLK is
selected. (If the CPU is powered down, the watchdog is disabled if WDCLK = 0, see
both WDTE and WDSE are set to 1, this bit is forced to 1.) Refer to
for details.
1
WDTOF
Watchdog Timer Time-Out Flag. This bit is set when the 8-bit down counter underflows. In watchdog mode,
a feed sequence will clear this bit. It can also be cleared by writing a logic 0 to this bit in software.
2
WDRUN Watchdog Run Control. The watchdog timer is started when WDRUN = 1 and stopped when WDRUN = 0.
This bit is forced to 1 (watchdog running) and cannot be cleared to zero if both WDTE and WDSE are set to
1.
3:4 -
reserved
5
PRE0
Clock Prescaler Tap Select. Refer to
for details.
6
PRE1
7
PRE2
Table 99.
Watchdog timeout vales
PRE2 to PRE0
WDL (in decimal)
Timeout Period
(in watchdog clock
cycles)
Watchdog Clock Source
400 KHz Watchdog
Oscillator Clock
(Nominal)
12 MHz CCLK (6 MHz
CCLK
⁄
2
Watchdog
Clock)
000
0
33
82.5
μs
5.50
μs
255
8,193
20.5 ms
1.37 ms
001
0
65
162.5
μs
10.8
μs
255
16,385
41.0 ms
2.73 ms
010
0
129
322.5
μs
21.5
μs
255
32,769
81.9 ms
5.46 ms
011
0
257
642.5
μs
42.8
μs
255
65,537
163.8 ms
10.9 ms
100
0
513
1.28 ms
85.5
μs
255
131,073
327.7 ms
21.8 ms
101
0
1,025
2.56 ms
170.8
μs
255
262,145
655.4 ms
43.7 ms
110
0
2,049
5.12 ms
341.5
μs
255
524,289
1.31 s
87.4 ms
111
0
4097
10.2 ms
682.8
μs
255
1,048,577
2.62 s
174.8 ms