NXP Semiconductors P89LPC9321 UM10310 - Manual (Page 47)

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User manual Rev. 2 — 1 November 2010 47 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
9. Capture/Compare Unit (CCU)
This unit features:
• A 16-bit timer with 16-bit reload on overflow
• Selectable clock (CCUCLK), with a prescaler to divide the clock source by any integer
between 1 and 1024.
• Four Compare / PWM outputs with selectable polarity
• Symmetrical / Asymmetrical PWM selection
• Seven interrupts with common interrupt vector (one Overflow, 2xCapture,
4xCompare), safe 16-bit read/write via shadow registers.
• Two Capture inputs with event counter and digital noise rejection filter.
9.1 CCU Clock (CCUCLK)
The CCU runs on the CCUCLK, which can be either PCLK in basic timer mode or the
output of a PLL (see
Figure 21 ). The PLL is designed to use a clock source between
0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and
32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider
(PLLDV3:0 bits in the TCR21 register) to help divide PCLK into a frequency between
0.5 MHz and 1 MHz.
9.2 CCU Clock prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow. Writing a value to
the prescaler will cause the prescaler to restart.
Table 32. Real-time Clock Control register (RTCCON - address D1h) bit description
Bit Symbol Description
0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1.
Note that this bit will not power-down the Real-time Clock. The RTCPD bit
(PCONA.7) if set, will power-down and disable this block regardless of RTCEN.
1 ERTC Real-time Clock interrupt enable. The Real-time Clock shares the same
interrupt as the watchdog timer. Note that if the user configuration bit WDTE
(UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an
interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the
Real-time Clock caused the interrupt.
2:4 - reserved
5 RTCS0 Real-time Clock source select (see Table 30 ).
6 RTCS1
7 RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock
reaches a count of logic 0. It can be cleared in software.