Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 101)

t
w(WAKE-INT)
t
d(WAKE-STBY)
t
d(IDLE−XCOH)
32 SYSCLKOUT Cycles
Wake−up
Signal
X1/XCLKIN
XCLKOUT †
STANDBY Normal Execution STANDBY
Flushing Pipeline
A
B
C
D
E
F
Device
Status
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake-up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device responds to the interrupt (if enabled).
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 6-14. STANDBY Entry and Exit Timing
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