Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 40)

C28x CPU
PIE
TIMER 2 (for RTOS)
TIMER 0
Watchdog
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
96 Interrupts
†
TINT0
Interrupt Control
XNMICR(15:0)
XINT1
Interrupt Control
XINT1CR(15:0)
XINT2
Interrupt Control
XINT2CR(15:0)
GPIO
MUX
WDINT
INT1 to INT12
INT13
INT14
NMI
XINT1CTR(15:0)
XINT2CTR(15:0)
XNMICTR(15:0)
TIMER 1 (for RTOS)
TINT2
Low-Power Modes
LPMINT
WAKEINT
XNMI_XINT13
MUX
TINT1
enable
select
† Out of a possible 96 interrupts, 45 are currently used by peripherals.
SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
3.6 Interrupts
Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device.
Figure 3-4. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F2812, 45 of these are used by peripherals as
shown in
Table 3-10 .
40 Functional Overview Copyright © 2009 – 2011, Texas Instruments Incorporated
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