19 spi master mode timing – Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 108
t
c(SPC)
+
SPI clock
cycle time
+
LSPCLK
4
or
LSPCLK
(SPIBRR
)
1)
+
t
c(LCO)
+
LSPCLK cycle time
GPIOxn
XCLKOUT
t
w(GPI)
(2)
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Figure 6-23. General-Purpose Input Timing
NOTE
The pulse width requirement for general-purpose input is applicable for the XBIO and
ADCSOC pins as well.
6.19 SPI Master Mode Timing
Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)
(1) (2) (3)
SPI WHEN (SPIBRR + 1)
SPI WHEN (SPIBRR + 1)
IS EVEN OR
IS ODD AND
NO.
UNIT
SPIBRR = 0 OR 2
SPIBRR
>
3
MIN
MAX
MIN
MAX
1
t
c(SPC)M
Cycle time, SPICLK
4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
–
0.5t
c(LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 0)
2
(4)
ns
Pulse duration, SPICLK low
t
w(SPCL)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
–
0.5t
c(LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 1)
Pulse duration, SPICLK low
t
w(SPCL)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
–
10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 0)
3
(4)
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
–
10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 1)
Delay time, SPICLK high to SPISIMO
t
d(SPCH-SIMO)M
–
10
10
–
10
10
valid (clock polarity = 0)
4
(4)
ns
Delay time, SPICLK low to SPISIMO
t
d(SPCL-SIMO)M
–
10
10
–
10
10
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
+ 0.5t
c(LCO
)
–
10
SPICLK low (clock polarity = 0)
5
(4)
ns
Valid time, SPISIMO data valid after
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
–
10
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
t
su(SOMI-SPCL)M
0
0
low (clock polarity = 0)
8
(4)
ns
Setup time, SPISOMI before SPICLK
t
su(SOMI-SPCH)M
0
0
high (clock polarity = 1)
Valid time, SPISOMI data valid after
t
v(SPCL-SOMI)M
0.25t
c(SPC)M
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
–
10
SPICLK low (clock polarity = 0)
9
(4)
ns
Valid time, SPISOMI data valid after
t
v(SPCH-SOMI)M
0.25t
c(SPC)M
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
–
10
SPICLK high (clock polarity = 1)
(1)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(3)
Not production tested.
(4)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
108
Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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