Texas Instruments Digital Signal Processor SM320F2812-HT User Manual

Page 96

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w(RSL1)

h(XPLLDIS)

h(XMP/MC)

h(boot-mode)

(See Note D)

DDIO

, V

DD3VFL

DDAn

, V

DDAIO

(3.3 V)

(See Note B)

XCLKIN

2.5 V

0.3 V

XRS

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

, V

DD1

(1.8 V (or 1.9 V))

XCLKOUT

I/O Pins

User-Code Dependent

Boot-ROM Execution Starts

Peripheral/GPIO Function
Based on Boot Code

GPIO Pins as Input

XPLLDIS Sampling

GPIOF14

XCLKIN/8 (See Note C)

GPIO Pins as Input (State Depends on Internal PU/PD)

OSCST

(Don’t Care)

User-Code Dependent

Address/Data/

Control

Address/Data Valid. Internal Boot-ROM Code Execution Phase

User-Code Execution Phase

NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V

and 3.3-V supply reaches 2.5 V.

B. V

DDAn

− V

DDA1

DDA2

and AV

DDREFBG

C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2

register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.

D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then

samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution
time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.

d(EX)

See Note A

su(XPLLDIS)

SM320F2812-HT

SGUS062B

–

JUNE 2009

–

REVISED JUNE 2011

www.ti.com

Figure 6-9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)

Electrical Specifications