Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 59)

Result Registers
EVB
S/W
ADCSOC
EVA
S/W
Sequencer 2 Sequencer 1 SOC SOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
Module
ADC
12-Bit
Analog
MUX
ADCINA0
ADCINA7
ADCINB0
ADCINB7
System
Control Block
High-Speed
Prescaler
HSPCLK ADCENCLK
C28x
SYSCLKOUT
S/H
S/H
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 4-4. Block Diagram of the F2812 ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins
( V
DDA1
/V
DDA2
, AV
DDREFBG
) from the digital supply. Figure 4-5 shows the ADC pin connections for the
F2812 device.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
ADCENCLK: On reset, this signal is low. While reset is active-low (XRS), the clock to the
register still functions. This is necessary to make sure all registers and modes go into
their default reset state. The analog module is in a low-power inactive state. As soon as
reset goes high, then the clock to the registers is disabled. When the user sets the
ADCENCLK signal high, then the clocks to the registers is enabled and the analog
module is enabled. There is a certain time delay (ms range) before the ADC is stable and
can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low,
the ADC module is powered. If high, the ADC module goes into low-power mode. The
HALT mode stops the clock to the CPU, which stops the HSPCLK. Therefore the ADC
register logic is turned off indirectly.
Copyright © 2009 – 2011, Texas Instruments Incorporated Peripherals 59
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT