Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 136)

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
Table 6-50. Sequential Sampling Mode Timing (1)
AT 25 – MHz ADC
SAMPLE n SAMPLE n + 1 CLOCK, REMARKS
t
c(ADCCLK)
= 40 ns
Delay time from event trigger to
t
d(SH)
2.5t
c(ADCCLK) sampling
(1 + Acqps) × Acqps value = 0-15
t
SH
Sample/Hold width/Acquisition width 40 ns with Acqps = 0
t
c(ADCCLK)
ADCTRL1[8:11]
Delay time for first result to appear
t
d(schx_n)
4t
c(ADCCLK)
160 ns
in the Result register
Delay time for successive results to (2 + Acqps) ×
t
d(schx_n+1)
80 ns
appear in the Result register t
c(ADCCLK)
(1) Not production tested.
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