Table 3-4, Table 3-5 – Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 35
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Table 3-4. Peripheral Frame 0 Registers
(1)
NAME
ADDRESS RANGE
SIZE (
×
16)
ACCESS TYPE
(2)
0x00 0880
Device Emulation Registers
384
EALLOW protected
0x00 09FF
0x00 0A00
reserved
128
0x00 0A7F
0x00 0A80
EALLOW protected
FLASH Registers
(3)
96
0x00 0ADF
CSM Protected
0x00 0AE0
Code Security Module Registers
16
EALLOW protected
0x00 0AEF
0x00 0AF0
reserved
48
0x00 0B1F
0x00 0B20
XINTF Registers
32
Not EALLOW protected
0x00 0B3F
0x00 0B40
reserved
192
0x00 0BFF
0x00 0C00
CPU-TIMER0/1/2 Registers
64
Not EALLOW protected
0x00 0C3F
0x00 0C40
reserved
160
0x00 0CDF
0x00 0CE0
PIE Registers
32
Not EALLOW protected
0x00 0CFF
0x00 0D00
PIE Vector Table
256
EALLOW protected
0x00 0DFF
0x00 0E00
Reserved
512
0x00 0FFF
(1)
Registers in Frame 0 support 16-bit and 32-bit accesses.
(2)
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3)
The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-5. Peripheral Frame 1 Registers
(1)
NAME
ADDRESS RANGE
SIZE (
×
16)
ACCESS TYPE
0x00 6000
256
Some eCAN control registers (and selected bits in
eCAN Registers
0x00 60FF
(128
×
32)
other eCAN control registers) are EALLOW-protected.
0x00 6100
256
eCAN Mailbox RAM
Not EALLOW-protected
0x00 61FF
(128
×
32)
0x00 6200
reserved
3584
0x00 6FFF
(1)
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Functional Overview
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