23 external interface read timing, Figure 6-29. example read access – Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 119
Lead
Active
Trail
DIN
t
d(XCOHL-XRDL)
t
d(XCOH-XA)
t
d(XCOH-XZCSL)
t
d(XCOHL-XRDH)
t
h(XD)XRD
t
d(XCOHL-XZCSH)
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.
t
su(XD)XRD
t
a(A)
t
a(XRD)
XREADY
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
6.23 External Interface Read Timing
Table 6-34. External Memory Interface Read Switching Characteristics
(1)
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
–
2
3
ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
t
d(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
1
ns
t
d(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
–
2
1
ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(2)
ns
t
h(XA)XRD
Hold time, address valid after XRD inactive high
(2)
ns
(1)
Not production tested.
(2)
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-35. External Memory Interface Read Timing Requirements
(1)
MIN
MAX
UNIT
t
a(A)
Access time, read data from address valid
(LR + AR)
–
14
(2)
ns
t
a(XRD)
Access time, read data valid from XRD active low
AR
–
12
(2)
ns
t
su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
12
ns
t
h(XD)XRD
Hold time, read data valid after XRD inactive high
0
ns
(1)
Not production tested.
(2)
LR = Lead period, read access. AR = Active period, read access. See
Figure 6-29. Example Read Access
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Electrical Specifications
119
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