Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 107)

t
d(XCOH-GPO)
GPIO
XCLKOUT
t
r(GPO)
t
f(GPO)
GPIO
Signal
1
Sampling Window QUALPRD
Output From
Qualifier
1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
SYSCLKOUT
QUALPRD = 1 (2 x SYSCLKOUT cycles) x 5
NOTES: A. This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00
to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value n, the qualification sampling period in 2n
SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin is sampled). Six consecutive samples must be of the
same value for a given input to be recognized.
B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs
should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur.
Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition.
See Note A
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 6-21. General-Purpose Output Timing
6.18 General-Purpose Input/Output (GPIO) – Input Timing
Figure 6-22. GPIO Input Qualifier – Example Diagram for QUALPRD = 1
Table 6-20. General-Purpose Input Timing Requirements (1)
MIN MAX UNIT
With no qualifier 2 × t
c(SCO)
t
w(GPI)
Pulse duration, GPIO low/high All GPIOs cycles
With qualifier 1 × t
c(SCO)
+ IQT (2)
(1) Not production tested.
(2) Input Qualification Time (IQT) = [5 × QUALPRD Ч 2] Ч t
c(SCO)
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