Figure 6-31, Continued) – Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 123
Lead
Active
Trail
DIN
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XZCSH)
t
d(XCOHL-XRDH)
WS (Synch)
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
XREADY(Synch)
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t
c(XTIM)
− t
su(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
t
h(XRDYsynchL)
t
su(XRDYsynchL)XCOHL
t
su(XD)XRD
t
a(XRD)
t
a(A)
t
h(XD)XRD
t
h(XRDYsynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
t
su(XRDHsynchH)XCOHL
See Note D
See Note E
t
e(XRDYsynchH)
See Note D
See Notes A and B
See Note C
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(continued)
MIN
MAX
UNIT
t
h(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
Figure 6-31. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
0 = XREADY
≥
1
3
≥
1
1
0
N/A
(1)
N/A
(1)
N/A
(1)
(Synch)
(1)
N/A =
"
Don
'
t care
"
for this example
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Electrical Specifications
123
Product Folder Link(s):