Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 141)

(n−2) Bit (n−1)
(n−3) (n−2) Bit (n−1)
(n−4) (n−3) (n−2) Bit (n−1)
M18
M17
M18
M17
M17
M18
M16
M15
M4
M4
M14
M13
M3, M12
M1, M11
M2, M12
(RDATDLY= 10b)
DR
(RDATDLY= 01b)
DR
(RDATDLY= 00b)
DR
FSR (ext)
FSR (int)
CLKR
M8
M7
M7
M8
M6
M7
M9
M10
(XDATDLY= 10b)
DX
(XDATDLY= 01b)
DX
(XDATDLY= 00b)
DX
(n−2) Bit (n−1) Bit 0
(n−4) Bit (n−1) (n−3) (n−2) Bit 0
(n−3) (n−2) Bit (n−1) Bit 0
M20
M14
M13
M3, M12
M1, M11
M2, M12
FSX (ext)
FSX (int)
CLKX
M5
M5
M19
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 6-41. McBSP Receive Timing
Figure 6-42. McBSP Transmit Timing
Copyright © 2009 – 2011, Texas Instruments Incorporated Electrical Specifications 141
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