Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 11)

SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Digital Signal Processor
Check for Samples: SM320F2812-HT
1 Features
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• High-Performance Static CMOS Technology • 128 Bit Security Key/Lock
– 150 MHz (6.67 ns Cycle Time) – Protects Flash/ROM/OTP and L0/L1 SARAM
– Low Power (1.8 V Core at 135 MHz, 1.9 V, – Prevents Firmware Reverse Engineering
Core at 150 MHz, 3.3 V I/O) Design • Three 32 Bit CPU Timers
– 3.3 V Flash Voltage • Motor Control Peripherals
• JTAG Boundary Scan Support (1) – Two Event Managers (EVA, EVB)
• High-Performance 32 Bit CPU (TMS320C28x) – Compatible to 240xA Devices
– 16 × 16 and 32 x 32 MAC Operations • Serial Port Peripherals
– 16 × 16 Dual MAC – Serial Peripheral Interface (SPI)
– Harvard Bus Architecture – Two Serial Communications Interfaces
– Atomic Operations (SCIs), Standard UART
– Fast Interrupt Response and Processing – Enhanced Controller Area Network (eCAN)
– Unified Memory Programming Model – Multichannel Buffered Serial Port (McBSP)
With SPI Mode
– 4M Linear Program Address Reach
• 12 Bit ADC, 16 Channels – 4M Linear Data Address Reach
– 2 × 8 Channel Input Multiplexer – Code-Efficient (in C/C++ and Assembly)
– Two Sample-and-Hold – TMS320F24x/LF240x Processor Source Code
Compatible
– Single/Simultaneous Conversions
• On-Chip Memory – Fast Conversion Rate: 80 ns/12.5 MSPS
– Flash Devices: Up to 128K × 16 Flash (Four • Up to 56 Individually Programmable,
8K × 16 and Six 16K × 16 Sectors) Multiplexed General-Purpose Input / Output
(GPIO) Pins
– ROM Devices: Up to 128K × 16 ROM
• Advanced Emulation Features – 1K × 16 OTP ROM
– Analysis and Breakpoint Functions – L0 and L1: 2 Blocks of 4K × 16 Each
Single-Access RAM (SARAM) – Real-Time Debug via Hardware
– H0: 1 Block of 8K × 16 SARAM • Development Tools Include
– M0 and M1: 2 Blocks of 1K × 16 Each – ANSI C/C++ Compiler/Assembler/Linker
SARAM – Supports TMS320C24x ™ /240x Instructions
• Boot ROM (4K × 16) – Code Composer Studio ™ IDE
– With Software Boot Modes – DSP/BIOS ™
– Standard Math Tables – JTAG Scan Controllers [Texas Instruments
• External Interface (TI) or Third-Party]
– Up to 1M Total Memory – Evaluation Modules
– Programmable Wait States – Broad Third-Party Digital Motor Control
Support
– Programmable Read/Write Strobe Timing
• Low-Power Modes and Power Savings – Three Individual Chip Selects
– IDLE, STANDBY, HALT Modes Supported • Clock and System Control
– Disable Individual Peripheral Clocks – Dynamic PLL Ratio Changes Supported
xxx – On-Chip Oscillator
xxx – Watchdog Timer Module
• Three External Interrupts xxx
• Peripheral Interrupt Expansion (PIE) Block That xxx
Supports 45 Peripheral Interrupts
xxx
xxx
(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
1
TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of
Texas Instruments.
2
eZdsp is a trademark of Spectrum Digital Incorporated.
Copyright © 2009 – 2011, Texas Instruments Incorporated Features 11