Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 130
See Note A
See Note B
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Table 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
(1) (2) (3) (4)
MIN
MAX
UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4t
c(XTIM)
+ t
c(XCO)
ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low
4t
c(XTIM)
+ 2t
c(XCO)
ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high
4t
c(XTIM)
ns
t
d(HH-BV)
Delay time, XHOLD high to Bus valid
6t
c(XTIM)
ns
(1)
When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance
state.
(2)
The state of XHOLD is latched on the rising edge of XTIMCLK.
(3)
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
(4)
Not production tested.
A.
All pending XINTF accesses are completed.
B.
Normal XINTF operation resumes.
Figure 6-36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
130
Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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