Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 5)

SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
List of Figures
2-1 SM320F2812 Die Layout ........................................................................................................ 14
2-2 SM320F2812 172-Pin HFG CQFP (Top View) ............................................................................... 15
3-1 Functional Block Diagram
.......................................................................................................
26
3-2 F2812 Memory Map (See Notes A. Through G.)
............................................................................
26
3-3 External Interface Block Diagram .............................................................................................. 38
3-4 Interrupt Sources ................................................................................................................. 40
3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 41
3-6 Clock and Reset Domains
......................................................................................................
44
3-7 OSC and PLL Block
..............................................................................................................
46
3-8 Recommended Crystal/Clock Connection .................................................................................... 47
3-9 Watchdog Module ................................................................................................................ 48
4-1 CPU-Timers ....................................................................................................................... 50
4-2 CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)
.................................................
51
4-3 Event Manager A Functional Block Diagram (See Note A.)
................................................................
56
4-4 Block Diagram of the F2812 ADC Module .................................................................................... 59
4-5 ADC Pin Connections With Internal Reference (See Notes A and B) ..................................................... 60
4-6 ADC Pin Connections With External Reference ............................................................................. 61
4-7 eCAN Block Diagram and Interface Circuit
...................................................................................
64
4-8 eCAN Memory Map
..............................................................................................................
65
4-9 McBSP Module With FIFO ...................................................................................................... 68
4-10 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 73
4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode) .......................................................... 76
4-12 GPIO/Peripheral Pin Multiplexing
..............................................................................................
79
5-1 28x Device Nomenclature
.......................................................................................................
81
6-1 SM320F2812-HT Life Expectancy Curve ..................................................................................... 86
6-2 Typical Current Consumption Over Frequency ............................................................................... 88
6-3 Typical Power Consumption Over Frequency ................................................................................ 89
6-4 F2812 Typical Power-Up and Power-Down Sequence – Option 2
........................................................
90
6-5 Output Levels
.....................................................................................................................
91
6-6 Input Levels ....................................................................................................................... 91
6-7 3.3-V Test Load Circuit .......................................................................................................... 92
6-8 Clock Timing ...................................................................................................................... 95
6-9 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)
...................................................
97
6-10 Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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98
6-11 Warm Reset in Microcomputer Mode .......................................................................................... 98
6-12 Effect of Writing Into PLLCR Register ......................................................................................... 98
6-13 IDLE Entry and Exit Timing ..................................................................................................... 99
6-14 STANDBY Entry and Exit Timing
.............................................................................................
101
6-15 HALT Wakeup Using XNMI
...................................................................................................
103
6-16 PWM Output Timing ............................................................................................................ 104
6-17 TDIRx Timing .................................................................................................................... 105
6-18 EVASOC Timing ................................................................................................................ 105
6-19 EVBSOC Timing
................................................................................................................
105
6-20 External Interrupt Timing
.......................................................................................................
106
6-21 General-Purpose Output Timing .............................................................................................. 107
6-22 GPIO Input Qualifier – Example Diagram for QUALPRD = 1 ............................................................. 107
6-23 General-Purpose Input Timing ................................................................................................ 108
Copyright © 2009 – 2011, Texas Instruments Incorporated List of Figures 5