Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 102)

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
Table 6-12. HALT Mode Switching Characteristics (1)
PARAMETER MIN TYP MAX UNIT
Delay time, IDLE instruction executed to XCLKOUT
t
d(IDLE-XCOH)
32 × t
c(SCO)
45 × t
c(SCO)
Cycles
high
t
w(WAKE-XNMI)
Pulse duration, XNMI wakeup signal 2 × t
c(CI)
Cycles
t
w(WAKE-XRS)
Pulse duration, XRS wakeup signal 8 × t
c(CI)
Cycles
t
p
PLL lock-up time 131 072 × t
c(CI)
Cycles
Delay time, PLL lock to program execution resume
– Wake-up from flash
t
d(wake)
1125 × t
c(SCO
) Cycles
– Flash module in sleep state
– Wake-up from SARAM 35 × t
c(SCO)
Cycles
(1) Not production tested.
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