Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 97
t
w(RSL)
t
h(XPLLDIS)
t
h(XMP/MC)
t
OSCST
V
DDIO
, V
DD3VFL
V
DDAn
, V
DDAIO
(3.3 V)
XCLKIN
X1
XRS
XF/XPLLDIS
XMP/MC
V
DD
, V
DD1
(1.8 V (or
1.9 V))
I/O Pins
XPLLDIS Sampling
Address/Data/
Control
XCLKOUT
(Don’t Care)
(Don’t Care)
GPIOF14/XF (User-Code Dependent)
XCLKIN/8 (See Note A)
(Don’t Care)
Input Configuration (State Depends on Internal PU/PD)
User-Code Dependent
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
User-Code Dependent
2.5 V
0.3 V
t
d(EX)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
See Note B
t
su(XPLLDIS)
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Figure 6-10. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Electrical Specifications
97
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