Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 41)

INT12
MUX
INT11
INT2
INT1
CPU
(Enable) (Flag)
INTx
INTx.8
PIEIERx(8:1) PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals or
External
Interrupts
(Enable) (Flag)
IER(12:1) IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts (1)
PIE INTERRUPTS CPU
INTERRUPTS INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
WAKEINT TINT0 ADCINT PDPINTB PDPINTA
INT1 XINT2 XINT1 reserved
(LPM/WD) (TIMER 0) (ADC) (EV-B) (EV-A)
T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT
INT2 reserved
(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)
CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT
INT3 reserved
(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)
T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT
INT4 reserved
(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)
CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT
INT5 reserved
(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)
MXINT MRINT SPITXINTA SPIRXINTA
INT6 reserved reserved reserved reserved
(McBSP) (McBSP) (SPI) (SPI)
INT7 reserved reserved reserved reserved reserved reserved reserved reserved
INT8 reserved reserved reserved reserved reserved reserved reserved reserved
ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
INT9 reserved reserved
(CAN) (CAN) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
INT10 reserved reserved reserved reserved reserved reserved reserved reserved
INT11 reserved reserved reserved reserved reserved reserved reserved reserved
INT12 reserved reserved reserved reserved reserved reserved reserved reserved
(1) Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However,
these interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
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