Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 44)

See Note A
SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
3.7 System Control
This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes.
Figure 3-6 shows the various clock and reset domains in the F2812 device that are
discussed.
A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3-6. Clock and Reset Domains
44 Functional Overview Copyright © 2009 – 2011, Texas Instruments Incorporated
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