12 low-power modes block – Texas Instruments Digital Signal Processor SM320F2812-HT User Manual

Page 49

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SM320F2812-HT

www.ti.com

SGUS062B

JUNE 2009

REVISED JUNE 2011

3.12 Low-Power Modes Block

The low-power modes on the F2812 are similar to the 240x devices.

Table 3-16

summarizes the various

modes.

Table 3-16. F2812 Low-Power Modes

MODE

LPM(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT

(1)

Normal

X,X

on

on

on

XRS,

WDINT,

IDLE

0,0

on

on

on

(2)

Any Enabled Interrupt,

XNMI

Debugger

(3)

XRS,

WDINT,

XINT1,

XNMI,

on

T1/2/3/4CTRIP,

STANDBY

0,1

off

off

(watchdog still running)

C1/2/3/4/5/6TRIP,

SCIRXDA,
SCIRXDB,

CANRX,

Debugger

(3)

off

XRS,

HALT

1,X

(oscillator and PLL turned off,

off

off

XNMI,

watchdog not functional)

Debugger

(4)

(1)

The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE
mode is not exited and the device goes back into the indicated low power mode.

(2)

The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.

(3)

On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

(4)

On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

The various low-power modes operate as follows:

IDLE Mode:

This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as long
as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

All other signals (including XNMI) wake the device from STANDBY mode if
selected by the LPMCR1 register. The user needs to select which signal(s)
wakes the device. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.

HALT Mode:

Only the XRS and XNMI external signals can wake the device from HALT
mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe
to use the XNMI signal for this function.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They
are in whatever state the code left them in when the IDLE instruction was executed.

Copyright

©

2009

2011, Texas Instruments Incorporated

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