Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 32)

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
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3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2812, 45 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)
The F2812 supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts
can be selected for negative or positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a
valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
3.2.12 Oscillator and PLL
The F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
The F2812 supports a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog generates a reset to the processor. The watchdog
can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the
event managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The F2812 device is a full-static CMOS device. Three low-power modes are provided:
IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively
and only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral wakes the processor from IDLE mode.
STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event wakes the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event.
32 Functional Overview Copyright © 2009 – 2011, Texas Instruments Incorporated
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