Ld a, i – Zilog Z08470 User Manual
Page 104
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Z80 Instruction Set
UM008007-0715
92
Z80 CPU
User Manual
LD A, I
Operation
A ← 1
Op Code
LD
Operands
A, I
Description
The contents of the Interrupt Vector Register I are loaded to the Accumulator.
Condition Bits Affected
S is set if the I Register is negative; otherwise, it is reset.
Z is set if the I Register is 0; otherwise, it is reset.
H is reset.
P/V contains contents of IFF2.
N is reset.
C is not affected.
If an interrupt occurs during execution of this instruction, the Parity flag contains a 0.
M Cycles
T States
MHz E.T.
2
9 (4, 5)
2.25
1
1
0
0
1
1
1
1
ED
0
1
1
1
1
1
0
0
57
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